View LTC3026EMSEPBF_4470895.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc3026 1 3026fe typical a pplica t ion fea t ures a pplica t ions descrip t ion 1.5a low input voltage vldo linear regulator the ltc ? 3026 is a very low dropout (vldo?) linear regula - tor that can operate at input voltages down to 1.14v. the device is capable of supplying 1.5a of output current with a typical dropout voltage of only 100mv. to allow opera - tion at low input voltages the ltc3026 includes a boost converter that provides the necessary headroom for the internal ldo circuitry. output current comes directly from the input supply to maximize efficiency. the boost converter requires only a small chip inductor and ceramic capacitor for operation. additionally, the boosted output voltage of one ltc3026 can supply the boost voltage for other ltc3026s, thus requiring a single inductor for multiple ldos. a user sup- plied boost voltage can be used eliminating the need for an inductor altogether. the ltc3026 regulator is stable with 10f or greater ceramic output capacitors. the device has a low 0.4v reference voltage which is used to program the output voltage via two external resistors. the device also has internal current limit, overtemperature shutdown, and reverse output current protection. the ltc3026 is avail - able in a small 10-lead msop or low profile (0.75mm) 10-lead 3mm 3mm dfn package. 1.2v output voltage from 1.5v input supply n input voltage range: 1.14v to 3.5v (with boost enabled) 1.14v to 5.5v (with external 5v boost) n low dropout voltage: 100mv at i out = 1.5a n adjustable output range: 0.4v to 2.6v n output current: up to 1.5a n excellent supply rejection even near dropout n shutdown disconnects load from v in and v bst n low operating current: i in = 950a at v in = 1.5v n low shutdown current: i in < 1a (typ), i bst = 0.1a (typ) n stable with 10f or greater ceramic capacitors n short-circuit, reverse current protected n overtemperature protected n available in 10-lead msop and 10-lead (3mm 3mm) dfn packages n high efficiency linear regulator n post regulator for switching supplies n microprocessor supply dropout voltage vs output current sw in 0.4v out bst 5v boost converter gnd adj pg l1 10h 4.7f c out 10f v in = 1.5v v out = 1.2v, 1.5a off on 100k 8.06k 4.02k ltc3026 3026 ta01a shdn l1: murata lqh2mcn100k02 + ? 4.7f i out (a) 0 dropout (mv) 100 150 3026 ta01b 50 0 0.5 1.0 1.5 1.2v 1.5v 2.0v 2.6v l , lt, ltc, ltm, linear technology, the linear logo and burst mode are registered trademarks and thinsot, vldo are trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc3026 2 3026fe a bsolu t e maxi m u m r a t ings v bst to gnd ................................................. C 0.3v to 6v v in to gnd ................................................... C 0.3v to 6v pg to gnd ................................................... C 0.3v to 6v shdn to gnd ............................................ C 0.3v to 6.3v adj to gnd .................................. C 0.3v to (v in + 0.3v) (note 1) top view dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 out out adj pg shdn in in gnd sw bst 11 gnd t jmax = 125c, v ja = 40c/w exposed pad (pin 11) is gnd, must be soldered to pcb 1 2 3 4 5 in in gnd sw bst 10 9 8 7 6 out out adj pg shdn top view mse package 10-lead plastic msop 11 gnd t jmax = 125c, v ja = 40c/w exposed pad (pin 11) is gnd, must be soldered to pcb p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range ltc3026edd#pbf ltc3026edd#trpbf lbhw 10-lead (3mm w 3mm) plastic dfn C40c to 125c ltc3026emse#pbf ltc3026emse#trpbf ltbjb 10-lead plastic msop C40c to 125c lead based finish tape and reel part marking package description temperature range ltc3026edd ltc3026edd#tr lbhw 10-lead (3mm w 3mm) plastic dfn C40c to 125c ltc3026emse ltc3026emse#tr ltbjb 10-lead plastic msop C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ output short-circuit duration .......................... in definite operating junction temperature range (note 8) ............................................. C 40c to 125c storage temperature range .................. C 65c to 125c lead temperature (mse, soldering, 10 sec) ......... 30 0c
ltc3026 3 3026fe e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t j = 25c. v in = 1.5v, v out = 1.2v, c in = c bst = 4.7f, c out = 10f (all capacitors ceramic) unless otherwise noted. (boost enabled, l sw = 10h) symbol parameter conditions min typ max units v in operating voltage (note 2) l 1.14 5.5 v i in operating current i out = 100a, v shdn = v in , 1.2v v in 5v l 95 200 a i inshdn shutdown current v shdn = 0v, v in = 3.5v l 0.6 20 a v bst boost operating voltage (note 7) v shdn = v in l 4.5 5 5.5 v v bstuvlo undervoltage lockout l 4.0 4.25 4.4 v i bst boost operating current i out = 100a, v shdn = v in l 175 275 a i bstshdn boost shutdown current v shdn = 0v 1 5 a the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t j = 25c. v in = 1.5v, v out = 1.2v, v bst = 5v, c in = c bst = 1f, c out = 10f (all capacitors ceramic) unless otherwise noted. (boost disabled, v sw = 0v or floating) symbol parameter conditions min typ max units v adj regulation voltage (note 5) 1ma i out 1.5a, 1.14v v in 3.5v, v bst = 5v, v out = 0.8v 1ma i out 1.5a, 1.14v v in 3.5v, v bst = 5v, v out = 0.8v l 0.397 0.395 0.4 0.4 0.403 0.405 v v out programming range l 0.4 2.6 v dropout voltage (note 6) v in = 1.5v, v adj = 0.38, i out = 1.5a l 100 250 mv i adj adj input current v adj = 0.4v l C100 100 na i out continuous output current v shdn = v in l 1.5 a i lim output current current limit 3 a e n output voltage noise f = 10hz to 100khz, i l = 800ma boost disabled boost enabled 110 210 v rms v rms the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t j = 25c. v in = 1.5v, v out = 1.2v, c in = c bst = 1f, c out = 10f (all capacitors ceramic) unless otherwise noted. (boost enabled or disabled) symbol parameter conditions min typ max units v in operating voltage (note 2) l 1.14 3.5 v i in operating current i out = 0ma, v out = 0.8v, v shdn = v in , v in = 1.2v i out = 0ma, v out = 1.2v, v shdn = v in , v in = 1.5v i out = 0ma, v out = 1.2v, v shdn = v in , v in = 2.5v i out = 0ma, v out = 1.2v, v shdn = v in , v in = 3.5v 1160 950 640 400 a a a a i inshdn shutdown current v shdn = 0v, v in = 3.5v l 0.6 20 a inductor size requirement inductor peak current requirement 4.7 150 10 40 h ma v bst boost output voltage range v shdn = v in 4.8 5 5.2 v v bstuvlo boost undervoltage lockout l 4.0 4.2 4.4 v boost output drive (note 3) v in < 1.4v v in 1.4v 7 10 ma ma
ltc3026 4 3026fe in supply current with boost converter enabled bst supply current with boost converter disabled in supply current with boost converter disabled typical p er f or m ance c harac t eris t ics elec t rical charac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. this ic has overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperatures will exceed 125c when overtemperature is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 2: minimum operating voltage required for regulation is: v in v out(min) + v dropout note 3: when using bst to drive loads other than ltc3026s, the load must be high impedance during start-up (i.e. prior to pg going high). note 4: pg threshold expressed as a percentage difference from the v adj regulation voltage as given in the table. note 5: operating conditions are limited by maximum junction temperature. the regulated output voltage specification will not apply for all possible combinations of input voltage and output current. when operating at maximum input voltage, the output current range must be limited. when operating at maximum output current, the input voltage range must be limited. note 6: dropout voltage is minimum input to output voltage differential needed to maintain regulation at a specified output current. in dropout, the output voltage will be equal to v in C v dropout . note 7: to maintain correct regulation v out v bst C 2.4v note 8: the ltc3026e is guaranteed to meet performance specifications from 0c to 125c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. note that the maximum ambient temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. 3026 g01 v in (v) 1.0 input current (ma) 1.50 1.25 1.00 0.75 0.50 0.25 0 1.5 2.0 2.5 3.0 3.5 ?40c 25c 85c 3026 g02 v in (v) 1.0 i bst (a) 5.5 4.0 4.5 5.0 1.5 2.0 2.5 3.53.0 200 150 100 50 0 ?40c 25c 85c 125c v bst = 5v 3026 g03 v in (v) 1.0 5.5 4.0 4.5 5.0 1.5 2.0 2.5 3.53.0 i in (a) 200 150 100 50 0 ?40c 25c 85c 125c v bst = 5v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t j = 25c. v in = 1.5v, v out = 1.2v, c in = c bst = 1f, c out = 10f (all capacitors ceramic) unless otherwise noted. (boost enabled or disabled) symbol parameter conditions min typ max units v ihshdn shdn input high voltage 1.14v v in 3.5v 3.5v v in 5.5v l l 1.0 1.2 v v v ilshdn shdn input low voltage 1.14v v in 5.5v l 0.4 v i ihshdn shdn input high current shdn = v in C1 1 a i ilshdn shdn input low current shdn = 0v C1 1 a v olpg pg output low voltage i pg = 2ma l 0.1 0.4 v i ohpg pg output high leakage current v pg = 5.5v 0.01 1 a pg output threshold (note 4) pg high to low pg low to high C12 C10 C9 C7 C6 C4 % %
ltc3026 5 3026fe adj voltage vs temperature in shutdown current bst voltage vs temperature typical p er f or m ance c harac t eris t ics dropout voltage vs input voltage ripple rejection ripple rejection shutdown threshold output current limit bst to out headroom voltage 3026 g04 temperature (c) ?50 ?25 404 403 402 401 400 399 398 397 396 75 100 0 5025 125 adjust voltage (mv) 1ma 1.5a v bst = 5v v in = 1.5v v out =1.2v 3026 g05 ?50 ?25 75 100 0 5025 125 temperature (c) input current (a) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1.2v 2.5v 3.5v 3026 g06 ?50 ?25 75 100 0 5025 125 temperature (c) 5.050 5.025 5.000 4.975 4.950 bst voltage (v) v in = 1.5v 3026 g07 v in (v) 1.2 200 180 160 140 120 100 80 60 40 20 0 2.2 1.4 1.6 1.8 2.4 2.0 2.6 dropout (mv) ?40c 25c 85c 125c v fb = 0.38v i out =1.5a 3026 g08 v in (v) 1.2 ripple rejection (db) 60 50 40 30 20 10 0 1.8 2.2 1.4 1.6 2.0 2.4 2.6 1mhz 100khz 10khz v bst = 5v v out =1.2v i out = 800ma c out = 10f 3026 g09 frequency (hz) 100 70 60 50 40 30 20 10 0 100000 1000 10000 1000000 1e+07 ripple rejection (db) v bst = 5v v in = 1.5v v out =1.2v i out = 800ma c out = 10f 3026 g10 v in (v) 1 v shdn threshold (mv) 1200 900 600 300 2 3 4 5 6 ?40c 25c 125c rise rise rise fall fall fall 3026 g11 v in (v) 1.0 i out (a) 2.5 3.5 1.5 2.0 3.0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 current limit thermal limit v out = 0v t a = 25c 3026 g12 temperature (c) ?50 v bst ? v out (v) 2.22 2.20 2.18 2.16 2.14 2.12 2.10 2.08 2.06 2.04 2.02 0 50 75 ?25 25 100 125
ltc3026 6 3026fe typical p er f or m ance c harac t eris t ics in supply transient response bst/out start-up bst ripple and feedthrough to out 3026 g16 v in 2v 1.5v v out ac 10mv/div 10s/div v out = 1.2v i out = 800ma c out = 10f v bst = 5v t a = 25c 3026 g17 shdn bst out hi lo 200s/div t a = 25c r out = 1 v in = 1.7v 5v 1.5v 1v 0v 3026 g18 v bst ac 20mv/div v out ac 5mv/div 20s/div v out = 1.2v v in = 1.5v i out = 1a c out = 10f l sw = 10h t a = 25c delay from enable to pg with boost disabled delay from enable to pg with boost enabled output load transient response 3026 g13 v in (v) 1.0 delay (s) 2.0 3.0 3.5 5.5 1.5 2.5 4.0 4.5 5.0 400 375 350 325 300 275 250 ?40c 25c 85c v out = 0.8v r out = 8 3026 g14 v in (v) 1.0 delay (ms) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 3.0 1.5 2.0 2.5 3.5 ?40c 25c 85c v out = 0.8v r out = 8 3026 g15 i out 1.5a 2ma out ac 20mv/div 50s/div v out = 1.5v c out = 10f v in = 1.7v v bst = 5v
ltc3026 7 3026fe p in func t ions in (pins 1, 2): input supply voltage. output load current is supplied directly from in. the in pin should be locally bypassed to ground if the ltc3026 is more than a few inches away from another source of bulk capacitance. in general, the output impedance of a battery rises with frequency, so it is usually advisable to include an input bypass capacitor when supplying in from a battery. a capacitor in the range of 0.1f to 4.7f is usually sufficient. gnd (pin 3, exposed pad pin 11): ground and heat sink. connect the exposed pad to the pcb ground plane or large pad for optimum thermal performance. sw (pin 4): boost switching pin. this is the boost converter switching pin. a 4.7h to 40h inductor able to handle a peak current of 150ma is connected from this pin to v in . the boost converter can be disabled by floating this pin or shorting this pin to gnd. this allows the use of an external boosted supply from a second ltc3026 or other source. see operating with boost converter disabled section for more information. bst (pin 5): boost output voltage pin. with boost con- verter enabled bypass the bst pin with a 4.7f low esr ceramic capacitor to gnd (c bst ). bst does not load v in when in shutdown, but is diode connected to in through the external inductor, thus, will not go to ground with v in present. users should not present any loads to the bst pin (with boost enabled) until pg signals that regulation has been achieved. when providing an external bst volt- age (i.e. boost converter disabled) a 1f low esr ceramic capacitor can be used. shdn (pin 6): shutdown input pin, active low. this pin is used to put the ltc3026 into shutdown. the shdn pin current is typically less than 10na. the shdn pin cannot be left floating and must be tied to a valid logic level (such as in) if not used. pg (pin 7): power good pin. when pg is high impedance out is in regulation, and low impedance when out is in shutdown or out of regulation. adj (pin 8): output adjust pin. this is the input to the error amplifier. it has a typical bias current of 0.1na flowing into the pin. the adj pin reference voltage is 0.4v referenced to ground. the output voltage range is 0.4v to 2.6v and is typically set by connecting adj to a resistor divider from out to gnd. see figure 2. out (pins 9, 10): regulated output voltage. the out pins supply power to the load. a minimum output capacitance of 5f is required to ensure stability. larger output capaci - tors may be required for applications with large transient loads to limit peak voltage transients. see the applica- tions information section for more information on output capacitance.
ltc3026 8 3026fe ? + ? + ? + ? + switching logic en shdn 0.4v reference boost converter 6 7 4 5 8 uvlo 1,2 sw in out bst shdn adj pg 9,10 0.372v 3026 bd gnd 3,11 + ? overshoot detect v off b lock diagra m
ltc3026 9 3026fe the ltc3026 is a vldo (very low dropout) linear regulator which operates from input voltages as low as 1.14v. the ldo uses an internal nmos transistor as the pass device in a source-follower configuration. the bst pin provides the higher supply necessary for the ldo circuitry while the output current comes directly from the in input for high efficiency regulation. the bst pin can either be supplied off-chip by an external 5v source or it can be generated through the internal boost converter of the ltc3026. boost converter operation for applications where an external 5v supply is not avail - able, the ltc3026 contains an internal boost converter to produce the necessary 5v supply for the ldo. the boost converter utilizes burst mode ? operation to achieve high efficiency for the relatively low current levels needed for the ldo circuitry. the boost converter requires only a small chip inductor between the in and sw pins and a small 4.7f capacitor at bst. the operation of the boost converter is described as fol- lows. during the first half of the switching cycle, an internal nmos switch between sw and gnd turns on, ramping the inductor current. a peak comparator senses when the inductor current reaches 100ma, at which point the nmos is turned off and an internal pmos between sw and bst turns on, transferring the inductor current to the bst pin. the pmos switch continues to deliver power to bst until the inductor current approaches zero, at which point the pmos turns off and the nmos turns back on, repeating the switching cycle. a burst comparator with hysteresis monitors the voltage on the bst pin. when bst is above the upper threshold of the comparator, no switching occurs. when bst falls below the comparators lower threshold, switching com - mences and the bst pin gets charged. the upper and lower thresholds of the burst comparator are set to maintain a 5v supply at bst with approximately 40mv to 50mv of ripple. care must be taken not to short the bst pin to gnd, since the body diode of the internal pmos transistor connects the bst and sw pins. shorting bst to gnd with an induc- tor connected between in and sw can ramp the inductor current to destructive levels, potentially destroying the inductor and/or the part. operating with boost converter disabled the ltc3026 has an option to disable the internal boost converter. with the boost converter disabled, the ltc3026 becomes a bootstrapped device and the bst pin must be driven by an external 5v supply, or driven by the bst pin of a second ltc3026 with the boost converter enabled. the recommended method for disabling the boost converter is to simply float the sw pin. with the sw pin floating no energy can be transferred to bst which effectively disables the boost converter. a second method for disabling the boost converter is to short sw to gnd. shorting sw to gnd to disable the boost converter should only be used in cases where in is in its specified operating range when the ltc3026 is enabled. enabling the part before v in is in its operating range can cause current to be pulled off bst with the sw pin grounded. this can cause current limited supplies to hang under the right conditions. connecting shdn to in will enable the part before in is in its specified operating range. with shdn connected to in the sw pin should be floated to disable the boost converter. either method of disabling the boost converter may be used if the signal driving the shdn pin is high only when in is in its specified operating range. connecting shdn to the power good pin of the supply driving in is one method that allows both disable methods to be used. a single ltc3026 boost converter can be used to drive multiple bootstrapped ltc3026s with the internal boost converters disabled. thus a single inductor can be used to power two (or possibly more) functioning ltc3026s. in cases where all ltc3026s have the same input supply (in) the internal boost converters of the bootstrapped ltc3026s can be disabled by shorting sw to gnd or float - ing the sw pin. if the ltc3026s are not all connected to the same input supply then the internal boost converters of the bootstrapped ltc3026s are disabled by floating the sw pin. if there is ever a doubt about which method to use remember that it is always safe to float the sw pin to disable the boost converter. there is no noticeable difference in performance of the part regardless of which disable method is used. o pera t ion
ltc3026 10 3026fe opera t ion figure 1. output load step response ldo operation an undervoltage lockout comparator (uvlo) senses the bst pin voltage to ensure that the bias supply for the ldo is greater than 4.2v before enabling the ldo. if bst is below 4.2v, the uvlo shuts down the ldo, and out is pulled to gnd through the external divider. the ldo provides a high accuracy output capable of supplying 1.5a of output current with a typical dropout voltage of only 100mv. a single ceramic capacitor as small as 10f is all that is required for output bypassing. a low reference voltage allows the ltc3026 output to be programmed to much lower voltages than available in common ldos (range of 0.4v to 2.6v). the devices also include current limit and thermal overload protection, and will survive an output short-circuit indefi - nitely. the fast transient response of the follower output stage overcomes the traditional trade-off between dropout voltage, quiescent current and load transient response inherent in most ldo regulator architectures, see figure 1. figure 2. soft-start with boost disable figure 3. programming the ltc3026 the ldo reference voltage from 0v to 0.4v over a period of approximately 200s, see figure 2. i out 1.5a 0ma out ac 20mv/div 100s/div v out = 1.5v c out = 10f v in = 1.7v v b = 5v 3026 f01 shdn out pg hi lo 100s/div t a = 25c r out = 1 v in = 1.7v v b = 5v 1.5v 1.5v 0v 0v 3026 f02 v out adj gnd c out r2 r1 ltc3026 3026 f03 v out = 0.4v 1 + r2 r1 ? ? ? ? ? ? the ltc3026 also includes a soft-start feature to prevent excessive current flow at v in during start-up. when the ldo is enabled, the soft-start circuitry gradually increases adjustable output voltage the output voltage is set by the ratio of two external resis- tors as shown in figure 3. the device servos the output to maintain the adj pin voltage at 0.4v (referenced to ground). thus, the current in r1 is equal to 0.4v/r1. for good transient response, stability and accuracy the current in r1 should be at least 80a, thus, the value of r1 should be no greater than 5k. the current in r2 is the current in r1 plus the adj pin bias current. since the adj pin bias current is typically <10na it can be ignored in the output voltage calculation. the output voltage can be calculated using the formula in figure 3. note that in shutdown the output is turned off and the divider current will be zero once c out is discharged.
ltc3026 11 3026fe o pera t ion the ltc3026 operates at a relatively high gain of 270v/a referred to the adj input. thus, a load current change of 1ma to 1.5a produces a 400v drop at the adj input. to calculate the change in the output, simply mul - tiply by the gain of the feedback network (i.e. 1 + r2/r1). for example, to program the output for 1.2v choose r2/r1 = 2. in this example an output current change of 1ma to 1.5a produces C400v ? (1 + 2) = 1.2mv drop at the output. power good operation the ltc3026 includes an open-drain power good (pg) output pin with hysteresis. if the chip is in shutdown or under uvlo conditions (v bst < 4.25v), pg is low im- pedance to ground. pg becomes high impedance when v out rises to 93% of its regulation voltage. pg stays high impedance until v out falls back down to 91% of its regula- tion value. a pull-up resistor can be inserted between pg and a positive logic supply (such as in, out, bst, etc.) to signal a valid power good condition. v in should be the minimum operating voltage (1.14v) or greater for pg to function correctly. output capacitance and transient response the ltc3026 is designed to be stable with a wide range of ceramic output capacitors. the esr of the output capacitor affects stability, most notably with small ca - pacitors. an output capacitor of 10f or greater with an esr of 0.05 or less is recommended to ensure stability. the ltc3026 is a micropower device and output transient response will be a function of output capacitance. larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. note that bypass capacitors used to decouple individual components powered by the ltc3026 will increase the effective output capacitor value. high esr tantalum and electrolytic capacitors may be used, but a low esr ceramic capacitor must be in parallel at the output. there is no minimum esr or maximum capacitor size requirements. extra consideration must be given to the use of ceramic capacitors. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. the most common di- electrics used are z5u, y5v, x5r and x7r. the z5u and y5v dielectrics are good for providing high capacitances in a small package, but exhibit strong voltage and tem- perature coefficients as shown in figures 4 and 5. when used with a 2v regulator, a 10f y5v capacitor can exhibit an effective value as low as 1f to 2f over the operating temperature range. the x5r and x7r dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. the x7r type has better stability across temperature, while the x5r is less expensive and is available in higher values. a minimum capacitance of 5f must be maintained at all times on the ltc3026 ldo output. figure 4. ceramic capacitor dc bias characteristics figure 5. ceramic capacitor temperature characteristics dc bias voltage (v) change in value (%) 3026 f04 20 0 ?20 ?40 ?60 ?80 ?100 x5r y5v both capacitors are 10f, 6.3v, 0805 case size 0 1 2 3 4 5 6 temperature (c) ?50 20 0 ?20 ?40 ?60 ?80 ?100 25 75 3026 f05 ?25 0 50 y5v change in value (%) x5r both capacitors are 10f, 6.3v, 0805 case size
ltc3026 12 3026fe opera t ion boost converter component selection a 10h chip inductor with a peak saturation current (i sat ) of at least 150ma is recommended for use with the internal boost converter. the inductor value can range between 4.7h to 40h, but values less than 10h result in higher switching frequency, increased switching losses, and lower max output current available at the bst pin. see table 1 for a list of component suppliers. table 1. inductor vendor information supplier part number website coilcraft 0603ps-103kb www.coilcraft.com murata lqh2mcn100k02 www.murata.com taiyo yuden lb2016t100m www.t-yuden.com tdk nlc252018t-100k www.tdk.com it is also recommended that the bst pin be bypassed to ground with a 4.7f or greater ceramic capacitor. larger values of capacitance will not reduce the size of the bst ripple much, but will decrease the ripple frequency propor - tionally. the bst pin should maintain 1f of capacitance at all times to ensure correct operation (see the output capacitance and transient response section about capacitor selection). high esr tantalum and electrolytic capacitors may be used, but a low esr ceramic must be used in parallel for correct operation. thermal considerations the power handling capability of the device will be limited by the maximum rated junction temperature (125c). the majority of the power dissipated in the device will be the output current multiplied by the input/output voltage differential: (i out )(v in C v out ). note that the bst current is less than 200a even under heavy loads, so its power consumption can be ignored for thermal calculations. the ltc3026 has internal thermal limiting designed to protect the device during momentary overload conditions. for continuous normal conditions, the maximum junction temperature rating of 125c must not be exceeded. it is important to give careful consideration to all sources of thermal resistance from junction to ambient. additional heat sources mounted nearby must also be considered. for surface mount devices, heat sinking is accomplished by using the heat-spreading capabilities of the pc board and its copper traces. copper board stiffeners and plated through holes can also be used to spread the heat gener - ated by power devices. a junction-to-ambient thermal coefficient of 40c/w is achieved by connecting the exposed pad of the msop or dfn package directly to a ground plane of about 2500mm 2 . calculating junction temperature example: given an output voltage of 1.2v, an input voltage of 1.8v 4%, an output current range of 0ma to 1a and a maximum ambient temperature of 50c, what will the maximum junction temperature be? the power dissipated by the device will be approximately: i out(max) (v in(max) C v out ) where: i out(max) = 1a v in(max) = 1.87v so: p = 1a(1.87v C 1.2v) = 0.67w even under worst-case conditions ltc3026 s bst pin power dissipation is only about 1mw, thus can be ignored. the junction to ambient thermal resistance will be on the order of 40c/w. the junction temperature rise above ambient will be approximately equal to: 0.67w(40c/w) = 26.8c the maximum junction temperature will then be equal to the maximum junction temperature rise above ambient plus the maximum ambient temperature or: t a = 26.8c + 50c = 76.8c short-circuit/thermal protection the ltc3026 has built-in output short-circuit current limiting as well as overtemperature protection. during short-circuit conditions, internal circuitry automatically limits the output current to approximately 3a. at higher
ltc3026 13 3026fe o pera t ion temperatures, or in cases where internal power dissipa- tion cause excessive self heating on-chip, the thermal shutdown circuitry will shut down the boost converter and ldo when the junction temperature exceeds approximately 150c. it will reenable the converter and ldo once the junction temperature drops back to approximately 140c. the ltc3026 will cycle in and out of thermal shutdown without latchup or damage until the overstress condition is removed. long term overstress (t j > 125c) should be avoided as it can degrade the performance or shorten the life of the part. reverse input current protection the ltc3026 features reverse input current protection to limit current draw from any supplementary power source at the output. figure 6 shows the reverse output current limit for constant input and output voltages cases. note: positive input current represents current flowing into the v in pin of ltc3026. with v out held at or below the output regulation voltage and v in varied, in current flow will follow figure 6s curves. i in reverse current ramps up to about 16a as the v in approaches v out . reverse input current will spike up as v in approaches within about 30mv of v out as the reverse current protection circuitry is disabled and normal opera - tion resumes. as v in transitions above v out the reverse current transitions into short-circuit current as long as v out is held below the regulation voltage. layout considerations connection from bst and out pins to their respec- tive ceramic bypass capacitor should be kept as short as possible. the ground side of the bypass capacitors should be connected directly to the ground plane for best results or through short traces back to the gnd pin of the part. long traces will increase the effective series esr and inductance of the capacitor which can degrade performance. with the boost converter enabled, the sw pin will be switching between ground and 5v whenever the bst pin needs to be recharged. the transition edge rates of the sw pin can be quite fast (~10ns). thus care must be taken to make sure the sw node does not couple capacitively to other nodes (especially the adj pin). additionally, stray capacitance to this node reduces the efficiency and amount of current available from the boost converter. for these reasons it is recommended that the sw pin be connected to the switching inductor with as short a trace as possible. if the user has any sensitive nodes near the sw node, a ground shield may be placed between the two nodes to reduce coupling. because the adj pin is relatively high impedance (depend - ing on the resistor divider used), stray capacitance at this pin should be minimized (<10pf) to prevent phase shift in the error amplifier loop. additionally special attention should be given to any stray capacitances that can couple external signals onto the adj pin producing undesirable output ripple. for optimum performance connect the adj pin to r1 and r2 with a short pcb trace and minimize all other stray capacitance to the adj pin. figure 6. input current vs input voltage figure 7. suggested layout 1 2 3 4 5 10 9 8 7 6 in in gnd sw bst out out adj pg shdn 3026 f07 via connection to gnd plane c in c out l sw c bst r2 r1 input voltage (v) i in current (a) 3026 f06 30 20 10 0 ?10 ?20 ?30 0 0.6 0.9 1.2 0.3 1.5 1.8 in current limit above 1.45v
ltc3026 14 3026fe typical a pplica t ions using 1 boost with multiple regulators 2.5v output from 3.3v supply with external 5v bias in sw out bst gnd adj pg 10h 4.7f c out1 10f v in = 2.5v v out1 1.8v, 1.5a pg1 pg2 100k 14k 4.02k ltc3026 3026 ta02 shdn ltc3026 with boost enabled fanout: 3-ltc3026 for v in <1.4v 5-ltc3026 for v in >1.4v * the sw pin of bootstrapped ltc3026 should be floated (disconnected from gnd) in cases where the bootstrapped ltc3026 does not share the same input supply (in) as the boosting ltc3026. boot strapped ltc3026 (boost disabled) 4.7f in sw* out bst gnd adj pg 1f c out2 10f v out2 1.5v, 1.5a 100k 11k 4.02k ltc3026 shdn 1f to additional regulators pg 3026 ta03 in sw* out bst gnd adj pg 1f c out 10f v out 2.5v, 1.5a 100k 21k 4.02k ltc3026 shdn 1f v bias = 5v n/c v in = 3.3v * see operating with boost converter disabled section for information on disabling boost converter.
ltc3026 15 3026fe p ackage descrip t ion msop (mse) 0910 rev g 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ? 0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1 2 3 4 5 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8910 10 1 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does not include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 1.68 0.102 (.066 .004) 1.88 0.102 (.074 .004) 0.50 (.0197) bsc 0.305 0.038 (.0120 .0015) typ bottom view of exposed pad option 1.68 (.066) 1.88 (.074) 0.1016 0.0508 (.004 .002) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref mse package 10-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1664 rev g)
ltc3026 16 3026fe p ackage descrip t ion 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev c 0310 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.70 0.05 3.55 0.05 package outline 0.25 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) pin 1 notch r = 0.20 or 0.35 45 chamfer
ltc3026 17 3026fe information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number d 3/10 addition to absolute maximum ratings changes to electrical characteristics changes to pin functions changes to operation section changes to typical applications additions to related parts 1 3, 4 7, 9 14, 18 18 e 5/11 remove i-grade in note 8. 4 (revision history begins at rev d)
ltc3026 18 3026fe linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2005 lt 0511 rev e ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments lt1761 100ma, low noise ldo in thinsot? 300mv dropout voltage, low noise: 20v rms , v in = 1.8v to 20v, thinsot package lt1762 150ma, low noise ldo 300mv dropout voltage, low noise: 20v rms , v in = 1.8v to 20v, ms8 package lt1763 500ma, low noise ldo 300mv dropout voltage, low noise: 20v rms , v in = 1.8v to 20v, so-8 package lt1764a 3a, fast transient response, low noise ldo 340mv dropout voltage, low noise: 40v rms , v in = 2.7v to 20v, to-220 and dd packages lt1844 150ma, very low dropout ldo 80mv dropout voltage, low noise <30v rms , v in = 1.6v to 6.5v, stable with 1f output capacitors, thinsot package lt1962 300ma, low noise ldo 270mv dropout voltage, low noise 20v rms , v in = 1.8v to 20v, ms8 package lt1963a 1.5a low noise, fast transient response ldo 340mv dropout voltage, low noise: 40v rms , v in = 2.5v to 20v, to-220, dd, sot-223 and so-8 packages lt1964 200ma, low noise, negative ldo 340mv dropout voltage, low noise 30v rms , v in = C1.8v to C20v, thinsot package lt1965 1.1a, low noise, low dropout linear regulator 290mv dropout voltage, low noise 40v rms , v in = 1.8v to 20v, to-220, ddpak, msop and 3mm w 3mm dfn packages ltc3025 300ma micropower vldo linear regulator 45mv dropout voltage, low noise 80v rms , v in = 0.9v to 5.5v, low i q : 54a, 2mm w 2mm 6-lead dfn package lt3080/lt3080-1 1.1a, parallelable, low noise, low dropout linear regulator 300mv dropout voltage (2 supply), low noise 40v rms , v in = 1.2v to 36v, v out = 0v to 35.7v, directly parallelable, to-220, sot-223, msop-8 and 3mm w 3mm dfn packages lt3150 fast transient response, vldo regulator controller 0.035mv dropout voltage via external fet, v in = 1.3v to 10v efficient, low noise 1.5v output from 1.8v dc/dc buck converter (ltc3026 boost converter disabled) i th run/ss sync/fcb v fb gnd sw in shdn gnd bst out adj pg sw sense ? v in tg bg ltc1773 10 9 8 7 6 1 2 3 4 5 r sense 0.04 33pf 200pf 30k 0.1f 1f 1f 80.6k 1% 100k 1% c in 47f 10v c out 10f c buck 47f 10v v buck 1.8v 2a 4.5v v in 5.5v si9942dy ltc3026 11k 100k 4.02k v out 1.5v 1.5a pg l1 2.5h 3026 ta04 c in , c buck : taiyo yuden lmk550bj476mm l1: cdrh5d28 r sense : irc lr1206-01-r040-f n/c

▲Up To Search▲

Price & Availability of LTC3026EMSEPBF

	To Download LTC3026EMSEPBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .